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LV5216CS
2) I 2 C bus transfer method
Start and stop conditions
During data transfer operation using the I 2 C bus, SDA must basically be kept in constant state while SCL is “H” as
shown below.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are set in the “H” state.
When SCL=SDA is “H,” the start condition is established when SDA is changed from “H” to “L,” and access is started.
When SCL is “H,” the stop condition is established when SDA is changed from “L” to “H,” and access is ended.
SCL
SDA
START condition
th1
STOP condition
ts3
Data transfer and acknowledgement response
After the start condition has been established, the data is transferred one byte (8 bits) at a time.
Any number of bytes of data can be transferred continuously.
Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side. The ACK signal is
issued when SDA on the send side is released and SDA on the receive side is set to “L” immediately after fall of the
clock pulse at the SCL eighth bit of data transfer to “L.”
When the next 1-byte transfer is left in the receive state after sending the ACK signal from the receive side, the receive
side releases SDA at the fall of the SCL ninth clock.
In the I 2 C bus, there is no CE signal. In its place, a 7-bit slave address is assigned to each device, and the first byte of
transfer is assigned to the command (R/W) representing the 7-bit address and subsequent transfer direction. Note that
only write is valid in this IC. The 7-bit address is transferred sequentially starting with MSB, and the eighth bit is set to
“L” which indicates a write.
In the LV5216CS the slave address is specified as "1110100"
Start
M
S
B
Slave address
L
S
B
W
A
C
K
M
S
B
Resister address
L
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
Stop
SCL
SDA
(WRITE)
SDA
(READ)
Start
M
S
B
Slave address
L
S
B
W
A
C
K
M
S
B
Data1
L
S
B
A
C
K
M
S
B
Data2
L
S
B
A
C
K
Stop
No.A1968-6/8
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